发明名称 MULTIPLE INSTRUCTION ISSUE COMPUTER ARCHITECTURE
摘要 A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decade result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.
申请公布号 CA2016068(C) 申请公布日期 2000.04.04
申请号 CA19902016068 申请日期 1990.05.04
申请人 发明人 HORST, ROBERT W.
分类号 G06F9/26;G06F9/38;(IPC1-7):G06F9/28;G06F9/22 主分类号 G06F9/26
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