发明名称 |
BUILT-IN TEST SCHEME FOR A JITTER TOLERANCE TEST OF A CLOCK AND DATA RECOVERY UNIT |
摘要 |
A jitter test system for a clock and data recovery unit (CRU) is comprised of a data generating apparatus, apparatus for clocking the data generating apparatus with a jittered clock, apparatus for applying a stream of data generated by the data generating apparatus that has been jittered by the jittered clock to an input of the CRU, and apparatus for detecting a bit error rate of a data signal output from the CRU. |
申请公布号 |
CA2179235(C) |
申请公布日期 |
2000.03.28 |
申请号 |
CA19962179235 |
申请日期 |
1996.06.17 |
申请人 |
|
发明人 |
DALMIA, KAMAL;IVANOV, ANDRE;GERSON, BRIAN DONALD;LAPADAT, CURTIS |
分类号 |
G01R31/30;G01R31/317;H04L1/20;H04L1/24;(IPC1-7):G06F11/25 |
主分类号 |
G01R31/30 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|