| 摘要 |
A memory chip containing a dual bank memory system is arranged to be mounted cross-wise in its package with the major axis of the memory chip extending along the minor axis of the package. The data output register and the chip bond pads are located between the two memory banks so that the data read/write lines extend only through a portion of the memory chip to the data output register. All of the address chip bond pads are located in one row and all of the data chip bond pads are located in another row that extends in parallel with the row of address chip bond pads. Also, the column decoder circuit for each memory bank is located at the center of the memory bank. This allows the column select lines to be segmented into two groups, with one group of column select lines extending from the center of the memory array outwardly toward one side of the memory array and with the other group of column select lines extending from the center of the memory array outwardly toward opposite side of the memory array. The memory architecture and layout provided by the invention reduces the length of the data read/write lines and the column select lines, with an attendant reduction in the RC time constant, allowing reduction in the memory access times.
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