| 摘要 |
A variable frequency dividing circuit adjusts the frequency dividing ratio by a non integer. The variable frequency dividing circuit includes a sequence storing part for storing an N-bit sequence data to output the N bits of the sequence data in parallel. The variable frequency dividing circuit also includes a sequence generator for receiving the N-bit sequence data from the sequence storing pan to generate a sequence control signal and a sequence control signal converter for converting the sequence control signal according to a frequency variation request to generate the converted sequence control signal. The variable frequency dividing circuit further includes a frequency divider for dividing a clock signal frequency according to the converted sequence control signal outputted from the sequence control signal converter and a clock signal generator for producing a clock waveform in accordance with the divided clock signal frequency.
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