| 摘要 |
PROBLEM TO BE SOLVED: To improve a reliability on checking a data transfer amount without adding a special circuit by adding one-bit data for recognition of final data to image data, checking the final data recognition bit with a timing whereat the final data is checked and checking the transfer amount of image data. SOLUTION: One that has a 9-bit bus width is used as a FIFO memory. A final data recognition bit is generated with a predetermined timing by a write data counter 2 of a final data recognition bit-generating circuit generating with a write timing to the memory, the number 3 of data to be written to the FIFO and a comparator 4. Information on the bit is written as a ninth bit data of image data to the memory with the same timing as the image data. The written image data is read from the memory synchronously with a send timing to an engine. The read image data including the final data recognition bit is sent to a final data-checking part in an engine I/F main control part and checked.
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