| 摘要 |
PROBLEM TO BE SOLVED: To provide a DRAM in which a well structure is simplified and the chip area is utilized. SOLUTION: Sub cell arrays MCA 1 and MCA 2 are formed on p-type wells PWC 1 and a PWC 2 respectively. A sense-amplifier circuit region SA arranged therebetween comprises three kinds of wells; a p-type well PW 1 isolated from the p-type wells PWC 1 and PWC 2, n-type well NWB 1, NWB 2 for separating these p-type wells. An NMOS sense-amplifier NSA is arranged in the p-type well PW 1, a PMOS sense-amplifier PSA and a changeover switch circuit Phit 1 are arranged in one of the n-type wells NWB 1, a bit line equalizing circuit EQL and a changeover switch circuit Phit 2 are arranged in the other n-type well NWB 2. |
