BIT LINE PRECHARGING AND EQUALIZING CIRCUIT IN A DYNAMIC RANDOM ACCESS MEMORY DEVICE

摘要

PURPOSE: A bit line precharging and equalizing circuit is provided to improve an operating speed of precharging and equalizing without increasing a layout. CONSTITUTION: The bit line precharging and equalizing circuit comprises a first and a second bit line precharging and equalizing circuits coupled between a plurality of the first and second bit line pairs and between adjacent pairs of the first and the second bit lines in which the first and second bit line precharging circuits precharge the first and second bit lines simultaneously.