Source-drain regions for sub-micron CMOS devices are formed using a reduced number of masking steps for forming a lightly p-doped drain region for a PMOS and a halo region for an NMOS

摘要

Source/drain region formation in a sub-micron CMOS process is achieved in a reduced number of masking steps for formation of a PLDD (lightly p-doped drain) region for a PMOS and a halo region for an NMOS, is new. Source/drain regions are formed in a substrate (100) having active NMOS and PMOS regions (120, 130) below gate electrodes (150, 155) by: (a) non-masked implantation of a first conductivity type dopant into the source/drain regions of the active zones; (b) formation of side wall spacers (180) on the gate electrodes; (c) application of a mask (190) which exposes only that active region (130) to be implanted with a second conductivity type dopant; (d) masked implantation of second conductivity type dopant into the exposed active region (130), with alignment by the side wall spacers (180), such that the second conductivity type dopant overcompensates the first conductivity type dopant; and (e) thermal treatment to drive the second conductivity type dopant under the side wall spacers. Preferred Features: The first conductivity type dopant is boron and the second conductivity type dopant is arsenic and/or phosphorus.