| 摘要 |
PROBLEM TO BE SOLVED: To suppress the increasing clock skews by receiving the clock data having a phase delayed compared with a control block and supplying a clock signal synchronized with an input clock signal after the phase adjustment to a memory element. SOLUTION: A phase adjustment circuit 29 receives the clock data as clock signals, distributes the clock signals which after the phase adjustment to the memory elements 26 via the supply lines 27 of same length, sets the delay value of a feedback circuit 28 at a level equal to that of the line 27 and supplies the clock signal that is synchronized with the leading edge of the input clock data and has no phase difference to every element 26. The clock data have a delay covering from a clock signal T1 through the input terminal of every circuit 29 led through an edge trigger type FF 21, a driver 22 and a supply line 31 and causes a phase difference between the clock signals used by a control block 13 and the element 26 respectively. Therefore, the block 13 and a storage block 25 keep a phase difference between them and operate synchronously with each other.
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