发明名称 DUAL GATE CMOS SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
摘要 PROBLEM TO BE SOLVED: To provide a dual gate CMOS semiconductor device, wherein the boron punch-through of a PMOS element and a short channel effect of an NMOS element are suppressed. SOLUTION: A dual-gate CMOS semiconductor device comprises a silicon semiconductor substrate 101, a P-well 102 and an N-well 103 formed on the silicon semiconductor substrate 101 respectively, a field oxide film 104 formed on the P-well 102 and the N-well 103, an NMOS transistor formed on the P-well 102, and a PMOS transistor formed on the N-well 103. The film thickness of a gate electrode 106a of an NMOS type element is smaller than that of a gate electrode 106b of a PMOS type element. The film thickness of the gate electrode 106a is 50-250 nm, while that of the gate electrode 106b is 100-350 nm. The film thickness of the gate electrode 106b is 1.5 times that of the gate electrode 106a or larger.
申请公布号 JP2000058668(A) 申请公布日期 2000.02.25
申请号 JP19980226884 申请日期 1998.08.11
申请人 SHARP CORP 发明人 NAKANO MASAYUKI;IWATA HIROSHI;KAKIMOTO SEIZO;MATSUOKA TOSHIMASA
分类号 H01L21/8238;H01L27/092;(IPC1-7):H01L21/823 主分类号 H01L21/8238
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