| 摘要 |
PROBLEM TO BE SOLVED: To restrain generation of latchup, by arranging a PMOS and an NMOS transistors which are usually kept on to a power source line connected with a memory cell and a GND line respectively, and leading noise to a board when noise is generated. SOLUTION: A PMOS transistor 13 is arranged in the way of a power source line 12 supplying a power source voltage VCC to a memory cell array 11, and an NMOS transistor 15 is arranged in the way of a GND line 14. The power source line 12 is connected with a PMOS transistor 13 which is usually on. When noise is generated in the power source voltage VCC, the noise is led from a source to an N-well region. The GND line 14 is connected with the NMOS transistor 15 which is usually on. When noise is generated in a ground potential, the noise is led from a source of the NMOS transistor 15 to a P-well region (board 16). As a result, the memory cell array 11 is prevented from invasion of noise, and generation of latchup can be restrained. |
