| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory with which the write time can be shortened, and further circuit complication and area increase can be prevented while suppressing an increase in the verify time and a normal read time. SOLUTION: All bit lines are charged up to a power source voltage Vcc level prior to write, each bit line is connected to a supply source of voltage according to the write data in accordance with levels of second storage nodes N23b, N22b, N21b of latch circuits Q23, Q22, Q21, and the write is performed in parallel. Also a read-out/verifying control circuit 23 is used jointly by data latch circuits 21-0 to 21-3, and each operation of write, verify, and read is performed cooperating with a corresponding data latch circuit by switching the connection with column switch groups 22-0 to 22-3 in which a conducting state is controlled by a column selection signal.</p> |
