| 摘要 |
PROBLEM TO BE SOLVED: To improve the accuracy of the timing check of a sequential circuit cell, to shorten verification man-hour at the time of logical simulation and to improve verification quality. SOLUTION: The terminal of an event transmission destination is judged, and when an event is transmitted to the clock terminal of the sequential circuit cell inside a circuit, a data terminal for which the minimum specification value of holding time is set to a negative value is detected, the event for which setup time is equal to or less than the absolute value of the minimum specification value of the holding time is detected and a logical operation is performed by using the inverted value of the state value (processing steps 21-23). The terminal of the event transmission destination is judged, and when the event is transmitted to the data terminal of the sequential circuit cell inside the circuit, it is detected that the minimum specification value of the setup time is set to the negative value and the holding time is equal to or less than the absolute value of the minimum specification value of the setup time and the logical operation is performed by using the state value at the present time (processing steps 24-26).
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