| 摘要 |
PROBLEM TO BE SOLVED: To make it possible to control and observe I/O signals to/from peripheral function macros at optional timing without increasing chip areas or the like even when the number of the peripheral function macros is increased by providing a CPU mega macro with a test bus interface to be functioned as a bus master for a system bus at the time of testing the peripheral function macros. SOLUTION: A test bus interface 21 is an interface between a test bus 12 for a mega macro separation test and a system bus 10. When a CPU mega macro 2 is selected as a target of the mega macro separation test, the interface 21 is then activated and functioned as a bus master of the system bus 10. By executing data accesses even to a peripheral macro groups 2 to 5 connected to the CPU mega macro 2 through the system bus 10, the test is executed to the respective peripheral macro groups 2 to 5 connected to the CPU mega macros 2 through the test bus interface 21. |
