RISC-MIKROPROZESSORARCHITEKTUR MIT SCHNELLEM UNTERBRECHUNGS- UND AUSNAHMEMODUS

摘要

Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.