发明名称 NEGATIVE BOOSTING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a negative boosting circuit which restrains the leakage and the substrate bias effect of a parasitic bipolar transistor and whose efficiency is good at a low voltage while the negative boosting circuit is constituted by using an N-channel MOS transistor. SOLUTION: When a negative boosting circuit is constituted by using N- channel MOS transistors 81 to 88 in a tripple well process, the substrate potential of the N-channel MOS transistors 81 to 88 is made to float. Thereby, a rise in the threshold of the transistors 81 to 88 due to a substrate bias effect is suppressed, and the collector current of a parasitic NPN transistor due to a forward current from a substrate caused by a boosting operation is suppressed. In addition, when the potential of a PW substrate in the start of the boosting operation is set at a ground potential by P-type MOS transistors 111 to 118, the substrate bias effect of the N-channel MOS transistors 81 to 88 is eliminated, and a boosting operation at 2 V or lower can be performed.</p>
申请公布号 JP2000011673(A) 申请公布日期 2000.01.14
申请号 JP19980172454 申请日期 1998.06.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ARIGA RIE
分类号 G11C16/06;G11C11/407;H01L21/822;H01L27/04;H02M3/07;(IPC1-7):G11C16/06 主分类号 G11C16/06
代理机构 代理人
主权项
地址