| 摘要 |
<p>PROBLEM TO BE SOLVED: To ensure a sufficient write time by controlling so that the source line potential becomes a specified power source potential in a specified period before the erase operation for the write operation to memory cells and previously charging gate capacitances of memory transistors of all on-cells on the same column as memory cells to write. SOLUTION: Before the write operation, the potential of a source line SL is once raised to a power source potential Vdd to previously charge gate capacitances of memory transistors MT2 of all on-cells on the same column as memory cells to write whereby if the source line SL is opened in the write operation for a first memory cell C1 to write, a booster circuit of a bit line BL does not charge the gate capacitance of a memory transistor MT2 of a second memory cell C2, i.e., an on-cell of other row on the same column through a first select transistor ST1 set on.</p> |
