Multilevel memory devices with multi-bit data latches

摘要

A multi-bit data latch includes a gated input buffer having a buffer input terminal, a buffer output terminal, and a buffer control terminal. The gated input buffer provides an output signal at the buffer output terminal responsive to an input signal applied to the buffer input terminal subject to a buffer control signal at the buffer control terminal. A first latch circuit has a first latch output terminal and a first latch input terminal, and a second latch circuit has a second latch output terminal and a second latch input terminal. A first switching circuit is operative to connect and disconnect the first latch input terminal to a reference voltage source responsive to an output signal at the buffer output terminal and to a first latch control signal. A second switching circuit is operative to connect and disconnect the second latch input terminal to the reference voltage source responsive to an output signal at the buffer output terminal and to a second latch control signal. A third switching circuit is operative to connect and disconnect the first latch output terminal to the reference voltage source responsive to an output signal at the buffer output terminal and to a third latch control signal. A reset circuit may be connected to the latch output terminals of the first and second latch circuits and operative to set the latch output terminals at a reference voltage source responsive to a reset signal.