Fabrication process for MOSFET devices and a reproducible capacitor structure

摘要

A process has been developed in which a capacitor structure can be simultaneously fabricated with NFET and PFET devices, to be used in EEPROM, SRAM or DRAM cells. The process features the use of a silicon nitride layer, protecting an underlying capacitor dielectric layer from an oxidation ambient, presented during a subsequent NFET source and drain drive-in procedure.