| 摘要 |
A system eliminates the adverse effects of serration and equalization pulses (periodically generated during the vertical sync interval) in regulating the frequency of horizontal sync pulses. These sync pulses provide timing information to regulate a video display. The system includes circuitry for stripping and processing the horizontal and vertical sync signals and the serration pulses from the video signals. These pulses are introduced to a first AND gate and through a first delay line to an input of a second AND gate. Frequency divider output signals are introduced to the first AND gate and to a third AND gate through a second delay line having an equal delay with the first delay line. The output from the first AND gate passes to second inputs of the second and third AND gates. The second and third AND gates produce signals which represent the time difference between the sync and divider output signals and which have a maximum time difference equal to the delays of the delay lines. In doing so, the gates eliminate the effects of the serration and equalization pulses. A phase comparator compares the times of occurrence of the second and third AND gate signals and introduces to a low pass filter the signals representing the time difference. A voltage controlled oscillator produces a signal having a frequency dependent upon the magnitude of the output voltage from the filter. The frequency of the oscillator signals is passed to a frequency divider. The resultant divider signals are introduced to the first AND gate and the second delay line.
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