发明名称 DEVICE AND METHOD FOR DESIGNING TEST PATTERN FOR VERIFICATION
摘要 PROBLEM TO BE SOLVED: To efficiently design and input the test pattern to verify the operation of an electronic circuit. SOLUTION: A test pattern design device for verification is provided with an input device 2 to give the input instruction of the signal to each terminal of an electronic circuit to verify the operation, a test pattern preparing means to prepare and control the test pattern in accordance with the input instruction from the input device 2, an operation device 3 to operate the test pattern design by various commands from the test pattern preparing means 5, and an output device 1 to indicate the screen of the table form (longitudinal: pattern number x transverse: table of terminal name) for inputting the test pattern which is the operational result of the operation device 3 and the screen of the waveform form (longitudinal: terminal name x transverse: time chart of the pattern number) of the input result. The signal of the test pattern is inputted from the input of the table form so as to design the test pattern based on the design process of the test pattern, and the input result is indicated on the screen by the waveform form.
申请公布号 JPH11344543(A) 申请公布日期 1999.12.14
申请号 JP19980154134 申请日期 1998.06.03
申请人 NEC COMMUN SYST LTD 发明人 KONDO SHUNSUKE
分类号 G01R31/3183;G06F11/22;G06F17/50 主分类号 G01R31/3183
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