| 摘要 |
<p>PROBLEM TO BE SOLVED: To prevent a delay of a CE access time from an address access time and speed up an entire chip in a semiconductor memory apparatus. SOLUTION: In consequence of a change of a CE signal, a CEa signal is input to each address input circuit 1. Upon receipt of a change of an address signal, ATD signals (node D) generated by ATD circuits 2 connected to outputs of the input circuits 1 do not contribute to the generation of a reference pulse CLKNEW, and therefore, a reference pulse generation timing, a pulse width at a CE access time do not change from those at an address access time. As a result, a conventional delay in access time only at the CE access time is eliminated. At the address access time, because of the change of the address signal not contributing to the generation of the reference pulse at the CE access time, signals (node D) generated by the ATD circuits 2 connected to outputs of the address input circuits 1 become conversely valid, thereby realizing an equivalent access time to a conventional access time.</p> |
