| 摘要 |
PROBLEM TO BE SOLVED: To enable a CPU to monitor abnormality of a clock signal operating a logic circuit without adding any clock for detection. SOLUTION: This clock operation monitor device is equipped with a counter 2 with a state number (n) which is arranged in a logic circuit 1 operating with a detected clock signal having cycles T1, a counter readout means 4 which is arranged in a logic circuit 3 operating with a clock signal other than the detected clock signal and reads the value of the counter 2 out in cycles T2 (T1<T2<T1×n), a counter value comparing means 5 which compares the value of the counter with a predicted value calculated on the basis of the last read value of the counter each time the counter is read, and a notifying means 7 which gives a notice of abnormality of the detected clock signal when it is judged that the value of the counter deviates from the predicted value.
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