发明名称 RESET CONTROL METHOD AND INFORMATION PROCESSING SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a reset system for guaranteeing the highly reliable operation continuance of a processor connected to a bus. SOLUTION: For this reset control method, respective controllers 20 and 70 connected through the host interface 40 of a SCSI(small computer system interface) bus or the like to the host computer 10 are provided with a bus connection state management table 26 for recording the using state of the bus, an instruction execution management table 27 for recording an instruction execution state at present and an interruption impossible instruction list 28. In the case that the host computer 10 issues a reset request to the controllers 20 and TO by using reset signals 41 so as to release the host interface 40, the respective controllers 20 and 70 decide the execution propriety of a reset processing according to the bus connection state management table 26 and the instruction execution management table 27. The controller performing a certain processing based on the interruption impossible instruction list 28 without using the host interface 40 does not perform the reset processing and safely continues an operation.
申请公布号 JPH11327695(A) 申请公布日期 1999.11.26
申请号 JP19980131684 申请日期 1998.05.14
申请人 HITACHI LTD;HITACHI SOFTWARE ENG CO LTD 发明人 MURATA KEISUKE;TAKAYASU ATSUSHI;KIDO KAZUYA;HIRATA KEIICHIRO
分类号 G06F11/14;G06F1/24 主分类号 G06F11/14
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