| 摘要 |
A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs). An inter-connect network provides routing of signals between the IOBs and VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. The IOBs are arranged along a top, left, bottom and right side of the plurality of VGBs. An IOB includes a 1) delay for timing input signals, 2) a configurable output latch which may be set or reset responsive to control signals, and 3) transistor for controlling a NOR line. The IOB is programmably configured to the inter-connect network which includes vertical and horizontal inter-connect channels comprising adjacent inter-connect lines. The IOB inputs are connected to adjacent inter-connect lines including 1) direct connect input lines from adjacent super-VGBs, 2) MaxL lines, and 3) dendrite lines from adjacent dendrites. The IOB outputs are connected to 1) MaxL lines, 2) dendrite lines in adjacent dendrites, 3) NOR lines, and 4) direct connect output lines to adjacent super-VGBs. Dendrites for routing signals along the periphery of the plurality of VGBs are positioned between the IOBs and super-VGBs. Dendrites include a plurality of I/O switchboxes and dendrite lines. The I/O switchboxes are coupled to vertical and horizontal inter-connect channels. The inter-connect network includes a direct connect architecture between IOBs and adjacent super-VGBs. Dedicated connections between corner and non-corner IOBs provide direct connect inputs and outputs to and from CBBs in a super-VGB.
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