| 摘要 |
<p>In the manufacture of integrated circuits with an embedded non-volatile memory, it is known to first provide the greater part of the memory and subsequently provide the CMOS logic in a second series of steps of a standard CMOS process. By virtue of this separation of process steps, it is possible to optimize the non-volatile memory substantially without degrading the logic. According to the invention, this process is further optimized in that, particularly for the periphery of the memory, and simultaneously with the memory transistors (21, 24, 27), transistors are manufactured which can cope with a higher voltage than the transistors of the logic. In the case of an EEPROM, each cell of the memory is provided with such a high-voltage transistor as a selection transistor (22, 24). Apart from the n-well implantation (5), high-voltage transistors of the p-channel are largely manufactured by means of the same process steps as the p-channel transistors in the logic, so that the number of process steps remains limited. By adding a single mask, the circuit may also be provided with a Flash or an OTP (One Time Programmable) memory.</p> |
