发明名称 |
High-speed phase-locked loop circuit |
摘要 |
The present invention designs and implements a high-speed PLL circuit and a high-speed synthesizer using the high-speed PLL circuit which has an increased switching speed, a reduced number of jitters and a reduced magnitude of spurious response. In order to achieve the above, the present invention provides a PLL circuit forming a closed loop wherein: one of the inputs of a phase comparator 1 serves as the input of the PLL circuit and the output of phase comparator 1 is connected to the input of a loop filter 2; the output of loop filter 2 is connected to the input of a voltage-controlled oscillator (VCO) 3; the output of the VCO 3 serves as the output of the PLL circuit; and the output of the VCO 3 is supplied to the other input of phase comparator 1 through a frequency divider 4. The circuit form and circuit constants of loop filter 2 are determined so that the transfer function of the closed loop becomes a Gaussian function.
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申请公布号 |
US5977838(A) |
申请公布日期 |
1999.11.02 |
申请号 |
US19970840019 |
申请日期 |
1997.04.24 |
申请人 |
HITACHI LTD. |
发明人 |
NAGOYA, YOSHINORI;ISHIDA, YUJI;TAKEI, KEN |
分类号 |
H03L7/089;H03L7/091;H03L7/093;H03L7/10;H03L7/183;(IPC1-7):H03L7/093 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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