发明名称 VARIABLE LENGTH CODE DETECTION IN A SIGNAL PROCESSING SYSTEM
摘要 A group of incoming data stream bits having packed variable length code ("VLC") words is applied to an entropy code bit length searching module. The group of bits is replicated within a plurality of matching modules selectively distributed among entropy code bit length searching logic units. Each unit of entropy code bit length searching logic supports a VLC word table as characterized by, for example, standard compression formats such as MPEG-1, MPEG-2, H.261, and H.263. The matching modules are divided into groups within the entropy code bit length searching logic units. A group of matching modules is allocated to each VLC bit length represented in the associated VLC word supported table. A number of matching modules are allocated to each bit length equal to a minimum number of patterns unique to VLC words of a particular bit length. The matching modules compare an incoming data group to respective patterns. A detected match is indicated by an appropriately set group output signal. Each entropy code bit length searching logic unit includes a bit length encoder that receives the group output signals. The set group output signal indicates the bit length of a current VLC, and the bit length encoder encodes this information into a bit length code output signal. The bit length code signal is utilized by a shifter to parse a corresponding bit length of current data. The parsed current data may be directly applied to an address generator which generates an output signal for a decoding look up table.
申请公布号 KR100227275(B1) 申请公布日期 1999.11.01
申请号 KR19970022662 申请日期 1997.06.02
申请人 SAMSUNG ELECTRONICS CO, LTD. 发明人 CHE, CHUL-SONN
分类号 H03M7/30;H03M7/00;H03M7/40;H03M7/42;H04N7/26;H04N7/50;(IPC1-7):H03M7/30 主分类号 H03M7/30
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