Synchronous semiconductor memory device including a circuit for arbitrarily controlling activation/inactivation timing of word line

摘要

An act signal generation circuit in a synchronous semiconductor memory device includes an act command latch circuit, an act command output circuit, and an act command control circuit. The act command latch circuit latches externally applied active command information. The act command output circuit responds to an enable signal to output an act initiation signal that renders a bank active. The act command control circuit responds to level transition of an external control signal in a test mode to alter the level of the enable signal. As a result, the active command information can be delayed and then transmitted to a bank.