| 摘要 |
A memory cell for a semiconductor device includes two pairs of a transfer transistor and a drive transistor at a first level and a pair of load transistors above the two pairs of transfer and drive transistors at a second level. Each of the load transistors includes a gate, a source/drain, and a channel. The cell further includes a pair of contacts extending between the first and second levels and that connect one of the gates to a respective one of the two pairs of transfer and drive transistors. Each load transistor gate includes a portion that overlies its respective channel and a lateral extension therefrom that contacts a respective one of the contacts. The extension of one load transistor gate overlaps the source/drain of the other load transistor adjacent the respective one of the contacts.
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