| 摘要 |
PROBLEM TO BE SOLVED: To variably set the minimum pulse width of a phase difference signal outputted from a phase comparator. SOLUTION: The leading edges of a reference signal Sref , and an oscillation signal Sosc are respectively detected by edge detection circuits 10a, 10b in the phase comparator 200 and detected results are inputted to SR flip flops(FFs) 30a, 30b respectively constituted of ECL circuits to set these FFs 30a, 30b. A reset signal is generated by a reset circuit constituted of an OR circuit OR1 and an inversion circuit INV5 in accordance with the states of the FFs 30a, 30b and the FFs 30a, 30b are set to a reset state, so that an UP signal Sup and a DOWN signal Sdw having prescribed width are generated in accordance with a phase difference between the reference signal Sref and the oscillation signal Sosc . Delay time required for delaying the reset signal by a delay circuit DL is variable. |
