| 摘要 |
PROBLEM TO BE SOLVED: To reduce a fixed pattern noise(FPN) level by using integrated successive correlation double sampling(SCDS) architecture. SOLUTION: Main blocks are a picture element block 100, a column block 140 and a chip output block 180. The main parts of the column block 140 are capacitors C1 and C2, a PMOS transistor P1, switches CDS and COL and current sources IPIXEL and ICOL. The chip output block 180 is constituted of a PMOPS transistor P2, a switch CHIP and a current source ICHIP in such a case. A plurality of column amplification circuits read a picture element circuit from an array column and they execute correlation double sampling operations through a single path. At least one accumulation device for canceling the fluctuation of a picture element is contained.
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