Circuit arrangement for automatic detection and removal of word-line and bit-line short circuits

摘要

The circuit arrangement provides automatic identification and elimination of word-line and bit-line short-circuits of a memory cell arrangement containing sensor amplifiers (SA). The sensor amplifiers (SA) divide the memory cell arrangements into memory banks. A fuse (FE) is provided in the bit-lines (BL1,BL2) in front of the sensor amplifiers (SA) in each memory bank. A transistor (T1) may be provided between the fuse (FE) and the sensor amplifier (SA) to actuate the fuse (FE). Alternatively, the fuse (FE) is actuated by applying a special voltage to the sensor amplifiers and/or applying an excess voltage to the word-line.