| 摘要 |
PROBLEM TO BE SOLVED: To generate a sampling clock with a same period as an interval of input video signal pixels at an optimum phase by obtaining a difference between a total pixel number of one horizontal synchronization period and a frequency division ratio of a PLL circuit through the use of phase information, setting a frequency divider ratio of a frequency divider accordingly and setting a phase of the sampling clock at an optimum phase position. SOLUTION: A discrimination circuit section 6 consisting of a microcomputer sets a phase change amount to a frequency divider ratio delay circuit of a frequency divider in a PLL circuit of a timing generator 7. Furthermore, based on address information at each point for one vertical synchronization period obtained by a maximum change point detection circuit 2, a left end point detection circuit 3 and a right end detection circuit 4, with a fixed frequency division ratio of the frequency divider, a phase change amount of the delay circuit is changed and a selector 5 selects a phase delay amount at a sampling point optimizing a sampling phase, the information is selected and acquired, and the discrimination section 6 discriminates whether or not the f-division ratio set to the PLL circuit of the timing generator 7 is coincident with a total pixel number for a period equivalent to one period of a horizontal synchronizing signal of the input video signal and whether or not the sampling lock phase is optimum. |
