| 摘要 |
<p>PROBLEM TO BE SOLVED: To prevent the malfunction of a nonvolatile semiconductor memory device and to enhance its yield. SOLUTION: When a memory cell in an even numbered row is written by a parity data signal O/E supplied to a selector 6, a first cell transistor 7 for correction whose structure is identical to that of the transistors in the even numbered row is selected. When a memory cell in an odd numbered row is written, a second cell transistor 8 for correction whose structure is identical to that of the transistors in the odd numbered row is selected. By a reference voltage Vref which is adjusted by the first cell transistor 7 for correction or the second cell transistor 8 for correction, the oscillation frequency of a VCO 1 is controlled, and the pulse width of a write enable pulseϕw to a row decoder 27 is changed. Consequently, by the write time to a memory cell, the amount of an electric charge injected into the floating gate of the memory cell is controlled, and a change in the characteristic of a nonvolatile semiconductor memory device is absorbed and eliminated.</p> |
