发明名称 Method and apparatus to reduce signal delay mismatch in a high speed interface
摘要 A device for compensating a signal delay introduced by a second circuit is provided. The second circuit is configured to receive a signal and to output the signal with the first delay if the first signal transitions from a first to a second logic level. The second circuit is configured to output the signal with the second delay if the first signal transitions from the second to the first logic level. The device according to the present invention includes a first circuit that is configured to receive the signal. The first circuit is configured to introduce the first delay, if the signal transitions from a second to a first logic level. The first circuit is configured to introduce the second delay if the signal transitions from the first to the second logic level.
申请公布号 US5949269(A) 申请公布日期 1999.09.07
申请号 US19970782601 申请日期 1997.01.13
申请人 INTEL CORPORATION 发明人 ALLEN, MICHAEL J.
分类号 H03K5/00;H03K5/135;H03K5/151;H03K19/003;(IPC1-7):H03K5/13 主分类号 H03K5/00
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