SIGNAL PROCESSOR

摘要

PROBLEM TO BE SOLVED: To prevent noise caused by the control clock signal of a digital signal circuit-side from being loaded on the power of an analog signal sampling circuit at the time of sampling the analog signal in the analog signal sampling circuit. SOLUTION: This signal processor is provided with a delay circuit 15 controlling delay time from outside. Delay is generated in mutual timings in the control clock signal DCLK of a digital signal circuit 14 side and the sampling control clock signal CTCLK of an analog signal sampling circuit 13 side and a phase is changed. Thus, noise caused by the control clock signal DCLK of a digital signal circuit 14 is prevented from being loaded on the analog signal sampling circuit 13-side.