| 摘要 |
A frequency synthesizer is supplied with an input signal of frequency fi to provide an output signal fo where fo=fi+E,fra M/N+EE and M and N are integers. The input signal is first applied to a divider circuit for division by +E,fra M/K+EE where K is an integer and the resultant is applied as inputs to a phase locked loop. The phase locked loop includes a ring oscillator of frequency fi+E,fra N/M+EE , a frequency multiplier circuit for multiplying by K, and a frequency divider circuit for dividing by N. The ring oscillator uses a combinational logic circuit that combines the outputs of four differential delay elements to produce a frequency multiplication of four.
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