| 摘要 |
A logic simulation system which comprises a connection data conversion section to convert the format of the connection data, a dump data generation section to generate and output the dump data, a data pattern generation section to generate and output the data pattern reflecting the chip inside variation, a clock pattern generation section to generate and output the clock pattern reflecting the chip inside variation, an expectation pattern generation section to generate and output the expectation pattern, a logic verification pattern generation section to synthesize the data pattern, the clock pattern and the expectation pattern and generates the logic verification pattern and an operation section to execute the logic simulation.
|
