| 摘要 |
A Viterbi decoder corresponding to PR IV system is composed of an even signal sequence processing circuit and an odd signal sequence processing circuit. A branch metric calculating circuit calculates branch metrics with an amplitude reference level R. In each of expressions for calculating the branch metrics, the number of adding operations is described to one or less. By averaging the number of calculations, the calculation speed of branch metrics can be increased. Thus, the overall process speed of the decoder can be increased. In addition, with a limitation of which the LSB of the reference level R is fixed to "0", the bit width of data to be calculated can be decreased. As a result, the number of adders, registers, and so forth can be decreased.
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