| 摘要 |
PROBLEM TO BE SOLVED: To prevent increase in a chip size and a reduction in transmission rate when a triple well process is used by a method, wherein drive circuits, which are respectively constituted of P-MOS transistors having different well bias voltages, are arranged independently of each other. SOLUTION: A DRV region 100a, 100b arranged between subword lien decoder regions 20 and a DRV region 100b arranged between SA regions 30 have a P-MOS transistor. A first P-MOS transistor which is applied with two well bias voltages, and a second P-MOS transistor which is applied with one well bias voltage, are respectively arranged on the regions 100a and 100b independently of each other. The regions 100a and 100b are arranged into a Z-shape with a memory region 100 as a reference. As a result, increase in the chip side due to an increase in the DRV regions 100a and 100b can be prevented. Moreover, in the case where drive circuits are arranged outside of the region 100, a signal delay which is induced due to the increase in the regions 100a and 100b, can be solved. |
