发明名称 |
Bild Prozessor und Verfahren |
摘要 |
<p>To enable high-speed write/read operation of image information in units of blocks, so as to fully meet the demand on high-speed operations such as MPEG etc, eight memory arrays MA1-MA8 are parallelly-connected in image memory unit 10; hence, in each memory array MAi, image information can be written/read individually under control of write address generating circuit 12, memory array control logic 14, and read address generating circuit 16. The input/output terminals of memory arrays MA1-MA8 are connected to half-bell operation circuit 24 through eight data registers DREG1-DREG8 of input/output buffer 18, eight row selectors YSEL1-YSEL8 and column selector XSEL of selector circuit 20, and data bus 22. <IMAGE></p> |
申请公布号 |
DE69325487(D1) |
申请公布日期 |
1999.08.05 |
申请号 |
DE1993625487 |
申请日期 |
1993.09.10 |
申请人 |
TEXAS INSTRUMENTS INC., DALLAS, TEX., US |
发明人 |
HASHIMOTO, MASASHI, MIHOMURA, INASHIKI-GUN, IBARAKI-KEN, JP;YAMAGUCHI, HIROHISA, TSUKUBA-SHI, IBARAKI-KEN, JP |
分类号 |
G09G3/20;G06T1/60;G06T9/00;G09G5/00;G09G5/36;G11C7/00;G11C11/401;H04N5/14;H04N5/907;H04N19/42;H04N19/423;H04N19/436;H04N19/50;H04N19/59;(IPC1-7):G06T9/00 |
主分类号 |
G09G3/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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