发明名称 Clock mode setting system of single chip type microcomputer
摘要 The external terminal (13A) performs the relay of external demand signal (ERA) input from the external to ICU (6). If the relay of CPU (15) is not performed, ICU outputs a control input signal to standard clock circuit (120) which materializes the two clock mode based on control input signal. The standard clock circuit supplies clock signal to CPU, ICU and memory (7). The ICU controls interruption of CPU in response to the input interruption demand signal. In usual mode, the standard clock supplier inputs clock to all circuits which operates in synchronization with clock. If the transition between the clock modes is performed in the low power consumption mode, the input of clock is stopped. The other external terminal performs relay of the external input signal input from the exterior as control input signal in signal line (65).
申请公布号 DE19842879(A1) 申请公布日期 1999.08.05
申请号 DE19981042879 申请日期 1998.09.18
申请人 MITSUBISHI DENKI K.K., TOKIO/TOKYO, JP 发明人 IKEMOTO, MASAHIKO, TOKIO/TOKYO, JP
分类号 G06F1/04;G06F1/32;G06F15/78;(IPC1-7):G06F1/32 主分类号 G06F1/04
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