发明名称 Repairable semiconductor intergrated circuit memory by selective assignmment of groups of redundancy elements to domains
摘要 <p>A method and apparatus for repairing a memory device through a selective domain redundancy replacement (SDRR) arrangement, following the manufacture and test of the memory device. A redundancy array supporting the primary arrays forming the memory includes a plurality of redundancy groups, at least one of which contains two redundancy units. A redundancy replacement is hierarchically realized by a domain that includes a faulty element within the redundancy group, and by a redundancy unit that repairs the fault within the selected domain. SDRR allows a domain to customize the optimum number and size redundancy units according to existing fault distributions, while achieving a substantially saving in real estate, particularly over the conventional flexible redundancy replacement, in term of the number of fuses (10-20%). By combining several types of redundancy groups, each having a different number of redundancy elements, full flexible redundancy replacement can also be achieved. Consequently, this approach compensates for the drawback of existing intra-block replacements, flexible redundancy replacements, and variable domain redundancy replacements, while improving repairability irrespective of the fault distribution within the memory device. &lt;IMAGE&gt;</p>
申请公布号 EP0933709(A2) 申请公布日期 1999.08.04
申请号 EP19990300702 申请日期 1999.01.29
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION;SIEMENS AKTIENGESELLSCHAFT 发明人 KIRIHATA, TOSHIAKI;PFEFFERL, KARL-PETER
分类号 G11C29/04;G11C29/00;(IPC1-7):G06F11/20 主分类号 G11C29/04
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