发明名称 Correlator and delay lock loop circuit
摘要 The present invention reduces the scale of circuitry and shortens the code phase detection time needed to achieve initial synchronization. In a correlator for calculating correlation between a received spreading code contained in a received spread-spectrum signal and a reference spreading code, a combined code generator is included. The combined code generator outputs a combined spreading code by weighting and combining a plurality of phase-shifted reference spreading codes A1-AM. Further, an arithmetic circuit calculates correlation between the received spreading code and the plurality of phase-shifted reference spreading codes simultaneously. A phase detection circuit detects the phase difference between the received spreading code and a reference spreading code, namely the phase of the received spreading code from the results of the arithmetic operation.
申请公布号 GB9913199(D0) 申请公布日期 1999.08.04
申请号 GB19990013199 申请日期 1999.06.07
申请人 FUJITSU LIMITED 发明人
分类号 H04B1/707;H04B1/7075;H04B1/7085;H04B1/709;H04B1/7095;H04L7/00 主分类号 H04B1/707
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