发明名称 Deadlock avoidance in a split-bus computer system
摘要 A mechanism is provided for avoiding deadlock in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, transactions begun on said split-transaction bus are monitored. When a combination of transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. The predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock. In accordance with another embodiment of the invention, the bus bridge detects when a state of the split-transaction bus would, if a protocol of said split-transaction bus were adhered to, result in deadlock. The bus bridge then drives one or more signals on the split-transaction bus in disregard of the protocol of the split-transaction bus, thereby avoiding deadlock. In accordance with still a further embodiment of the invention, transactions accepted within the bus bridge are monitored. When a combination of said transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. The predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock.
申请公布号 US5933612(A) 申请公布日期 1999.08.03
申请号 US19970903412 申请日期 1997.07.30
申请人 APPLE COMPUTER, INC. 发明人 KELLY, JAMES D.;REGAL, MICHAEL L.
分类号 G06F13/16;(IPC1-7):G06F13/00 主分类号 G06F13/16
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