发明名称 |
METHOD AND APPARATUS FOR ARITHMETIC OPERATION |
摘要 |
An arithmetic operation apparatus for determining a cumulative sum of products, which produces a result from a plurality of separate input data items without carrying out any transfer or addition of data so that a smaller number of operation cycles may be required. Input data X and Y are processed through a first decoder (511), a first selector (521), a first partial product generator (531) and first full adder (541) in order to provide the product of higher bits of the data X and Y. The input data X and Y are also processed through a second decoder (512), a second selector (522), a second partial product generator (532) and second full adder (542) in order to provide the product of lower bits of the data X and Y. The results are supplied to a shifter (55) for an adjustment of the number of shifts. The output from the shifter is processed through a third full adder (56) and a carry propagation adder (58) to provide a cumulative sum of products, or data Z, which is fed back to the input of the third full adder (56).
|
申请公布号 |
WO9938088(A1) |
申请公布日期 |
1999.07.29 |
申请号 |
WO1999JP00237 |
申请日期 |
1999.01.21 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;KANAKOGI, TOMOCHIKA;NAKAJIMA, MASAITSU |
发明人 |
KANAKOGI, TOMOCHIKA;NAKAJIMA, MASAITSU |
分类号 |
G06F7/52;G06F7/533;G06F7/544;(IPC1-7):G06F17/10 |
主分类号 |
G06F7/52 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|