| 摘要 |
<p>An image sensor device comprising a silicon substrate having a plurality of CMOS circuit formed thereon, including a pixel array having a plurality of rows and a plurality of columns, a row addressing circuit operatively connected to each the pixel array and the timing control circuit, the row addressing circuit having a row bus that provides address lines to each row in the pixel array, a column addressing circuit, a pixel timing circuit, a timing control logic block, a signal processing circuit, and an interface circuit coupled to external computational means for provision of address and control signals to the sensor device, the interface circuit being operatively coupled the timing control logic, the pixel timing circuit, the row addressing circuit and the column addressing circuit. <IMAGE></p> |
