| 摘要 |
Described is a computer system (10) having a multi-channel architecture wherein a plurality of individual channels (40AA,...,40ZZ) having a respective channel memory (50AA,...,50ZZ) and being connected by a bus (60). According to the invention, loading data, and preferably sequential data, into a channel memory (50AA) of one (40AA) of the plurality of individual channels (40AA,...,40ZZ) is accomplished by (a) loading data into the channel memory (50AA) to be loaded; (b) distributing further data which is to be loaded into the channel memory (50AA) to be loaded into another channel memory (50AB,...,50ZZ) of another one of the plurality of individual channels (40AB,...,40ZZ); and (c) reloading the data from the channel memory (50AB,...,50ZZ) of the other one of the plurality of individual channels (40AB,...,40ZZ) to the channel memory (50AA) to be loaded via the bus (60). The invention is preferably used in a testing system, such as an IC tester. <IMAGE> |
