发明名称
摘要 <p>PURPOSE:To obtain a moving image processor having high operation efficiency, small hardware size and inexpensive production cost by dividing a processing screen area, directly connecting an image memory and an output data buffer to respective processors and dividedly arranging respective parts in accordance with the divided areas. CONSTITUTION:When respective unit processor modules 1A, 2A require the image data of adjacent module areas 211 in order to execute movement compensation or the like in the area of a shared memory 14, the access of the memory 14 is requested by a flag signal 204 and the input processing of image data necessary for the area 211 is executed in accordance with a control signal 205 outputted from a control circuit 17. Since the requiring rate of the charged area image data of the adjacent module for the area 211 is sufficiently small in the image data of one frame, the modules 1A, 1B are temporarily stopped by an external interruption during the processing. Thereby, the generation of invalid time can be reduced and highly efficient processing can be attained. In this constitution, arbitration between respective modules can be reduced and the quantity of data transfer can be sharply reduced.</p>
申请公布号 JP2918601(B2) 申请公布日期 1999.07.12
申请号 JP19900040792 申请日期 1990.02.21
申请人 MITSUBISHI DENKI KK 发明人 YANAGISAWA KYOAKI
分类号 H04N19/42;G06T7/20;H04N7/15;H04N7/24;H04N9/77;H04N11/04;H04N19/00;H04N19/423;H04N19/426;H04N19/436;H04N19/503;H04N19/60;H04N19/61;H04N19/94;(IPC1-7):H04N7/24 主分类号 H04N19/42
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